1. Field of the Invention
The present invention relates to a PCI-E automatic allocation system, and more particularly, to a system applied in a computer system to allocate lanes for PCI-E buses.
2. Description of the Prior Art
With constant advancement of electronic and computer technology, resultant computer functions are not only increasingly powerful but also subject to upgrades or supplements emerging in the presence of new accompanying peripherals. However, upon the introduction of any new accompanying peripheral, the computer has to be restarted in order to finalize the installation of the peripheral, and in consequence it necessitates interrupting current operations. The aforesaid practice is both intricate and inconvenient, and it could have a devastating consequence, such as data loss or service interruption, especially in the case of those devices with strict persistence and reliability requirements, for example, servers.
Accordingly, early on, the industry put forth a technology, Peripheral Component Interconnection (hereinafter referred to as PCI), characterized by its hot swap function to serve as an I/O interface for a computer. PCI, a bus standard widely supported by computer systems nowadays, is an interconnection mechanism specially designed for peripherals with high bulk density, expansion cards, and processor/memory systems, and configured to incorporate various expansion cards, hard disks or CD-ROMs into a system and provide two-way communication between two devices, as well as between a device and a system memory/processor. Its most important feature is that it enables users to update, change or add PCI peripherals without turning off or suspending the operating system but in an online manner instead, and apply an update, change or addition without restarting the operating system. As a result, it greatly reduces scheduled or nonscheduled suspension duration, maximizes its availability, and greatly enhances computer performance.
An interface developed and released by Intel over a decade ago, the known PCI bus is operated in a 33 MHz, 32-bit environment, with a peak theoretical bandwidth of 132 MB per second. It uses a shared bus topology—bus bandwidth is shared among multiple devices—to enable communication among the different devices on the bus. As devices evolved, new bandwidth hungry devices began starving other devices on the same shared bus. Gigabit LAN cards, for example, can monopolize up to 95% of available PCI bus bandwidth. As a result, networking speed is inevitably compromised. More badly, with other computer accessories being upgraded, current PCI technology is becoming less fit to meet the computer system requirements, thus prompting the advent of a new technology which will substitute for the existing PCI technology and supply more bandwidth to a computer system.
To provide the bandwidth required by these modem devices, PCI Express was developed by an industry consortium of PC and peripheral vendors and began shipping in standard desktop PCs in 2004. Already, most desktop machines from the leading suppliers include at least one PCI Express (hereinafter referred to as PCI-E) slot. Compared to PCI, PCI-E performs data transmission by means of serial connection, point-to-point connection, and Low Voltage Differential Signaling (LVDS), and its advantages are, namely enhanced data transmission and reduced noise. With PCI-E standard technology, a basic PCI-E connection is defined as two LVDS pairs, one for sending signals, the other for receiving signals. Connection as such is defined as a lane, which enables 250 MBytes/s bandwidth per direction, per lane. The more lanes there are, the greater is the bandwidth provided by PCI-E.
Also, unlike PCI which divides bandwidth between all devices on the bus, PCI-E provides each device with its own dedicated data pipeline. Data is sent serially in packets through pairs of transmit and receive signals called lanes, Multiple lanes can be grouped together into ×1 (“single-lane”), ×2, ×4, ×8, ×12, ×16, and ×32 lane widths to increase bandwidth allocated to the slot. PCI-E dramatically improves data bandwidth compared to legacy buses, minimizing the need for onboard memory and enabling faster data streaming.
As mentioned above, the bandwidth provided by PCI-E depends on the number of PCI-E lanes available. For instance, as regards computer-specific motherboards nowadays, in general, it is the design of a hardware circuit which specifies the way in which PCI-E lanes are connected to the PCI-E slots of a computer-specific motherboard to determine a fixed bandwidth that PCI-E provides for each PCI-E slot. For instance, where a PCI-E ×4 slot and a PCI-E ×8 slot are installed on a computer-specific motherboard, and a PCI-E bus is associated with eight lanes which are evenly allocated to the PCI-E ×4 slot and the PCI-E ×8 slot, to facilitate the fast data streaming carried out between the memory of a computer and the dedicated lanes of the expansion cards inserted in the PCI-E ×4 slot and the PCI-E ×8 slot. However, in a situation where an expansion card is inserted in the PCI-E ×8 slot rather than the PCI-E ×4 slot, the aforesaid rule, that is, the PCI-E lanes being evenly allocated to the PCI-E ×4 slot and the PCI-E ×8 slot, makes the lanes associated with PCI-E ×4 slot idle, and in consequence part of the PCI-E lanes are not efficiently used; hence, resultant disadvantages are, namely slow data transmission, a waste of I/O bandwidth of the PCI-E bus, and inflexible PCI-E bus design.
Accordingly, an issue that currently confronts the industry and needs urgent solution involves developing a PCI-E automatic allocation technology to promote efficient use of PCI-E lanes and overcome the drawbacks of the prior art, such as inefficient use of PCI-E lanes arising out of inflexible allocation of PCI-E lanes, slow data transmission, and inflexible PCI-E bus design.